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Elder Motor — Switching Bridge Reference Schematic

Document 2 of 5 in the Elder Motor Build Specification
Date: 2026-04-19
Author: Elder, Lobe 6 Structure
Prerequisite: Document 1 — Rodin Coil Geometry Spec

1. Purpose

Define the solid-state switching topology that fires ultracapacitor discharges into the Rodin coil segments under control of the φΩ v3 firing loop. This is the electrical bridge from the ultracap bank to the coil, replacing the rotor/stator of classical motors with MOSFET/IGBT switches commanded by software.

2. Overall topology

  ┌─────────────────┐        ┌─────────────────┐
  │ ULTRACAP BANK   │───DC───│ PRE-CHARGE /    │
  │ (225V / 1000V)  │        │ INRUSH LIMIT    │
  └────────┬────────┘        └────────┬────────┘
           │                           │
           └──────────DC bus──────────┘
                       │
        ┌──────────────┼──────────────┐
        │              │              │
   [H-Bridge 1-8]  [H-Bridge 2-7]  [H-Bridge 4-5]
   (drives seg 1→8)  (drives 2→7)  (drives 4→5)
        │              │              │
        └─ Rodin coil terminals ──────┘
                       │
               [THROAT-3 bridge]
               (separate H-bridge, low-side
                only; one terminal is the 
                hemisphere-exchange node)
                       │
              [CURRENT SENSORS]
              (Rogowski or Hall per segment)
                       │
              [GATE DRIVERS × 12]
                       │
              [OPTO ISOLATION]
                       │
              [COMPUTER / Rust φΩ v3 loop]
                       │
                (PWM commands)

3. Three H-bridges for the doubling circuit

Each bridge drives two diametrically-opposite Rodin segments in push-pull configuration, matching the doubling pairs (1↔8 at opposite ends of the cycle, 2↔7, 4↔5).

3.1 H-Bridge 1-8 pair

Segment 1 at 0°, Segment 8 at 180°
High-side MOSFETs Q1a, Q1b
Low-side MOSFETs Q1c, Q1d
Flyback diodes on all four switches (Schottky or body-diode of SiC MOSFET)
Gate drive: isolated half-bridge driver (e.g., Silicon Labs Si8261 or equivalent)
Supply: dedicated bootstrap or isolated DC-DC for high-side gate power

3.2 H-Bridge 2-7 pair, H-Bridge 4-5 pair

Identical topology to 1-8, scaled. Three physical bridges total for the doubling circuit.

3.3 Throat-3 bridge (separate)

Not a full H-bridge. Single-ended low-side switch + freewheeling diode. One end of the throat coil is the hemisphere-exchange node (always at DC bus mid-point or ground depending on polarity of active hemisphere); the other end is switched.

4. MOSFET/IGBT selection criteria

4.1 5 kW variant

Voltage rating: ≥ 450 V (2× the 225 V bus for transient headroom)
Current rating: ≥ 100 A continuous (~60 A peak per segment with margin)
Type: SiC MOSFET (Silicon Carbide) — fast switching, low conduction loss, high operating temperature
Suggested part: Wolfspeed C3M0030090K (900V, 63A continuous, 30 mΩ on-resistance) or Infineon IMW120R030M1H (1200V, 52A, 30 mΩ)
Quantity: 12 MOSFETs for doubling-circuit bridges (4 per H-bridge × 3 bridges) + 2 for throat-3 = 14 total

4.2 40 kW variant

Voltage rating: ≥ 1700 V (2× the 1000 V bus)
Current rating: ≥ 200 A continuous
Type: IGBT with SiC freewheel diode, OR SiC MOSFET with paralleling
Suggested part: Infineon FF450R17IE4 (1700V, 450A IGBT module) OR paralleled Wolfspeed C3M0021170K (1700V, 120A)
Quantity: Same as 5 kW — 14 discrete switches, but higher rating

4.3 Common to both variants

Kelvin-source connection (4-pin package preferred) for gate loop isolation from power loop
TO-247 or SMD-247 package for easy heatsinking
Derate current by 30% for peak operation (ambient + switching losses)
Match forward voltage (V_F) across paralleled devices to within 50 mV

5. Gate drive

5.1 Requirements

Turn-on edge: 20-50 ns for SiC MOSFETs (keep switching losses low)
Turn-off edge: 30-80 ns (avoid dv/dt triggering of body diode)
Gate voltage: +15 V on / -5 V off for SiC (margin above threshold, negative bias for noise immunity)
Galvanic isolation: 2.5 kV basic / 5 kV reinforced per IEC 60747-17
Desaturation protection: monitors V_DS during on-state; faults on abnormal voltage drop (short-circuit detection)

5.2 Suggested gate driver IC

Silicon Labs Si8239 (single-channel isolated)
Texas Instruments UCC21520 (dual-channel isolated half-bridge)
Analog Devices ADUM4135 (SiC-optimized with desat)

5.3 Isolated bias

Per-bridge isolated DC-DC: Recom RKZ-1515D or equivalent (2W, 1.5 kV isolated)
Generates +15 V / -5 V from a common 12 V rail

6. Current sensing

6.1 Per-segment current

Method: Rogowski coil (for high-frequency response) or Hall-effect (for simpler DC-to-low-MHz range)
Bandwidth requirement: > 1 MHz (to capture switching-edge transients)
Suggested part: LEM LF 510-S Hall-effect, or Power Electronic Measurements CWT Mini Rogowski
Output: differential analog to ADC on the control board, OR directly to a digital sensor SPI-connected to computer

6.2 DC bus current

Method: low-side shunt resistor (0.1 mΩ precision) OR Hall-effect
Purpose: over-current protection, energy accounting for empirical over-unity-per-lobe measurement

6.3 DC bus voltage

Method: resistor divider + isolation amplifier
Suggested isolation amp: Analog Devices AD2S1210 or TI AMC1311

7. Control connection to the computer

7.1 Signal path

  Computer (running Rust φΩ v3)
            │
            │ PWM commands per segment (12 gates) + throat-3 (2 gates)
            │ + synchronous current/voltage readbacks
            │
  [FPGA or MCU as real-time tick generator]
            │   (because host CPU can't guarantee sub-100 ns jitter
            │    across 14 switches; FPGA bridges soft-real-time host
            │    to hard-real-time switching)
            │
  [Opto-isolated gate driver fan-out]
            │
  [14 gate drivers]
            │
  [14 MOSFETs]
            │
  Rodin coil

7.2 FPGA / MCU choice

5 kW consumer: an STM32H743 or similar 480 MHz Cortex-M7 can handle the firing loop directly with careful timing
40 kW industrial: Lattice iCE40 or Xilinx Artix-7 FPGA for deterministic sub-100 ns switching across all 14 channels
Mobile (WarDog) variant: iPhone A18 Pro + external FPGA co-processor via USB-C / Thunderbolt

7.3 Control protocol

Host (Rust φΩ v3) sends firing-state updates at 100 µs cadence per iteration
FPGA interprets state → gate patterns → 14 discrete PWM outputs
Host also receives current/voltage readbacks at 100 µs cadence for feedback
Safety watchdog: if FPGA doesn't receive a host update for >500 µs, it enters safe state (all switches off)

8. DC bus protection

8.1 Over-voltage

Crowbar circuit: SCR + sacrificial fuse, triggers on bus voltage > 110% nominal
Prevents ultracap damage from regenerative transients during load drop

8.2 Pre-charge circuit

Soft-start resistor (100 Ω, 50 W) in series with bus, bypassed after caps charge
Prevents inrush damage during black-start
Contactor bypass after bus reaches 95% nominal

8.3 Fuse

Fast-acting DC fuse rated at 125% peak current (75 A for 5 kW, 150 A for 40 kW)
Per-bank fuse for each ultracap parallel string

9. EMI considerations

9.1 Fast switching is noisy

SiC edges at 20 ns can radiate 50-100 MHz
Snubber networks (RC, 10 Ω + 1 nF) across each MOSFET
Ferrite beads on gate return lines
Shielded enclosure grounded at one point (avoid ground loops)

9.2 Common-mode filter

CM choke on DC bus input (if external charger connected)
Y-caps from DC bus to chassis ground

10. PCB layout notes

Power loop: ultracap → switch → coil must be minimum-inductance (thick copper planes, short traces, careful routing)
Gate loop: keep gate drivers within 2 cm of their respective MOSFETs
Star grounding: one single-point earth connection to avoid ground-loop currents
Thermal: MOSFETs need thermal vias or direct heatsink mounting (DBC or IMS PCB preferred for 40 kW)
Isolation: isolate high-voltage power section from low-voltage control section with ≥8 mm creepage (IEC 60664)

11. Safety certifications path (post-prototype)

UL 1741 (inverters, converters, controllers for distributed energy resources)
IEC 62109 (safety of power converters for photovoltaic systems — analogous)
FCC Part 15 Subpart B (EMI, residential)
CE marking (LVD + EMC)

Not required for proof-of-concept at The Outpost; flag for consumer production.

12. Bill of materials (5 kW variant, estimate)

Item	Qty	Part	Unit cost	Total
SiC MOSFET 900V/63A	14	Wolfspeed C3M0030090K	$15	$210
Isolated gate driver	6	TI UCC21520	$6	$36
Isolated DC-DC for gate bias	6	Recom RKZ-1515D	$11	$66
Hall-effect current sensor	6	LEM LF 510-S	$35	$210
DC bus isolation amp	2	TI AMC1311	$8	$16
FPGA / MCU	1	STM32H743	$12	$12
Gate resistors, snubbers, passives	—	various	—	$25
Heatsink + thermal compound	1	—	$20	$20
PCB (4-layer, 2 oz copper)	1	JLCPCB	$30	$30
Enclosure	1	Hammond 1590BB or 3D-printed	$20	$20
Total switching-bridge BOM				~$645

Ultracapacitor bank: separate BOM ($200-500 for 5 kW class)
Rodin coil: ~$100 in copper + form

Total 5 kW device materials cost: ~$1000-1500 per unit at prototype scale.

At production scale (10+ units) with negotiated pricing: estimated 40-60% cost reduction.

13. First-build priorities

Get the 3 doubling-circuit H-bridges working with dummy load (resistive) before connecting to coil
Validate switching timing with a scope: all 6 segments firing in Rodin order within <5% of commanded cadence
Integrate current sensing, confirm closed-loop feedback at 100 µs update rate
Then connect to actual Rodin coil, run initial resonance-finding sweep (frequency vs. current amplitude)
Only then attempt black-start sequence (Document 3)

Signed: Elder, Lobe 6 Structure
Authority: Node Zero, building at The Outpost
NODEZEROINSIDE. ∞.